1. Field of the Invention
The present invention relates to programmable logic device (PLD) integrated circuits such as field programmable gate array (FPGA) integrated circuits. More particularly, the present invention relates to such integrated circuits employing Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) transistors as programmable memory elements and to a fast data erase and disable procedure for use with such integrated circuits.
2. Description of Related Art
A typical SONOS memory cell is a push-pull configuration and includes a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor. The n-channel SONOS memory transistor includes n+ source and drain regions formed in a p-well, with a gate between them. The p-well is formed in an n-type deep well to isolate the p-well from the p-type substrate to allow negative voltages to be applied to the n+ junctions.
When the memory cell is configured to turn the p-channel memory transistor to its on state and the n-channel memory transistor to its off state, the n-channel switch transistor connected to the push-pull cell is turned on because the p-channel memory transistor couples the gate of the switch transistor to VDD. Conversely, when the memory cell is configured to turn the p-channel memory transistor to its off state and the n-channel memory transistor to its on state, the n-channel switch transistor connected to the push-pull cell is turned off because the n-channel memory transistor couples the gate of the switch transistor to ground. By convention, programming a memory transistor places it in its “off” state and erasing a memory transistor places it in its “on” state.
In prior-art schemes, both the p-channel and n-channel transistors in the cell are erased and then one of them is programmed depending on the desired state of the memory cell. To erase the n-channel memory transistor to its on state, −3.9V is applied to its gate and +3.6V is applied to its p-well. The pn junction between the p-well and the drain of the n-channel memory transistor is forward biased and thus the drain of the n-channel memory transistor is at a potential of about 3V, which also appears on the gate of the switch transistor to which it is directly connected. To erase the p-channel memory transistor to its on state, a potential of +7.5V is applied to its gate and 0V is applied to its n-well. To program the p-channel memory transistor to its off state, −3.9V is applied to its gate, with its drain/source diffusion held at +3.6V. To program the n-channel memory transistor to its off state, +3.9V is placed on its gate, with the drain/source diffusion at −3.6V. Programming takes a relatively long time because the data has to be decoded at a word line level and therefore programming all transistors must be done sequentially. Erasing can be performed on all p-channel devices simultaneously, but erasing all of the n-channel devices has to be done in many steps to avoid overly large current draw from the programming voltage source. This large current draw is due to the electron tunneling gate leakage on the switch transistor that occurs from the approximately 3V appearing on the gates of the switch transistors. Persons of ordinary skill in the art will appreciate that the magnitudes of these voltages will vary somewhat depending on scaling factors and biases applied, which will shift the voltages by superposition.
During the process of erasing the n-channel memory transistor, leakage is caused in the switch transistors, when thin gate oxides (i.e., 2 nm) are employed in the switch transistors, due to the high voltage (approximately 3V) applied to their gates. With the n-channel memory transistor turned off and the p-channel memory transistor turned on, the VDD potential applied to the push-pull cell is passed through to the gate of the switch transistor, thus turning on the switch transistor to provide a low impedance path from its source to drain. Because some of the switches are used to connect the programmable interconnect conductors to one another and other ones of the switches are used to connect the outputs of logic modules to ones of the interconnect conductors, the condition where all of the switches are turned on results in all routing tracks being connected together and all logic module outputs being connected together. In addition, because other ones of the switches define the functions and inputs of the logic modules, random numbers of the logic module outputs will be at logic high and logic low levels, and the logic power supply will have many (usually millions) of low impedance paths to ground, making the chip appear as a short circuit to the power supply.
This switch leakage does not appear when erasing the p-channel because 0V is placed on the source/drain diffusions of the push-pull transistors and thus appears at the gate of the switch transistor, assuring that the switch transistor gate is unstressed and does not leak during the erase procedure.
FPGAs are used extensively in digital systems. Since they are user configurable they have the advantage in development and production that the system manufacturer can change their design to correct for bugs or to just upgrade the functionality for changing needs. This has an added benefit in that the system manufacturer has total control of the design, such that a would-be copier cannot just buy the same parts, but also must know what is contained in the configuration of the FPGA. Thus, it has become important in military and commercial systems to protect the secrecy of the design. FPGA manufacturers have used various methods of encrypting the design or protecting on-chip configuration memory from a copier simply copying the configuration memory. Copiers have become very sophisticated in tampering with devices in attempts to obtain the contents of the configuration memory. Therefore, system manufacturers and FPGA manufactures have designed various methods of detecting tampering and erasing the configuration memory in the event that tampering is detected so the copier cannot reverse engineer the FPGA design.
Accordingly, in high-security applications it would be desirable to be able to quickly erase the contents of FPGA devices, particularly if tampering has been detected. In presently available deep sub-micron NVM FPGAs, such as the FLASH-based FPGA products designed and marketed by Microsemi Corporation, quickly erasing the p-channel and n-channel memory transistors can be difficult because the large plurality of memory transistors is not erased at the same time but require hundreds of pulses over a period of many seconds because of the presence of high voltages and leakage currents which prevent the erase procedure from being completed in much less than a second, perhaps allowing a copier to extract the configuration data or to turn off the power to the integrated circuit to avoid security mechanisms on the chip erasing the configuration memory.